1. Field of the Invention
The present invention relates to a semiconductor memory device in which a memory cell such as a 6-transistor SRAM (Static Random Access Memory) cell has a CMOS (Complementary Metal Oxide Semiconductor) structure. More particularly, the invention relates to a semiconductor memory device suitable for a split word line type SRAM in which word lines are arranged so as to be isolated from every word transistor.
2. Description of the Related Art
An SRAM cell generally comprises a flip-flop and two transistors (word transistors) which are made conductive or nonconductive in accordance with a voltage applied to a word line to determine whether each of two storage nodes of the flip-flop is connected to a bit line or not. The SRAM cells can be broadly divided into two types depending on a load element of the flip-flop; an MOS transistor load type and a high-resistance load type. The MOS transistor load type has the structure comprising six transistors. According to the type of the load transistor, there are a known p-channel type MOS transistor (hereinbelow, referred to as pMOS) load type and a known TFT (Thin Film Transistor) load type.
[Related Art 1]
FIG. 27 is a plan view showing an example of an arrangement pattern of a pMOS load type SRAM cell 300 of a related art. The diagram illustrates a state after gates of transistors are formed. An upper wiring layer of connecting lines, bit lines, and the like in the cell is omitted here. Instead, in FIG. 27, connecting lines of parts connected by the upper wiring layer are shown on the pattern.
The pMOS load type SRAM cell 300 has two p-type active regions 302a and 302b in which n-channel type MOS transistors (hereinbelow, referred to as nMOS transistors) are formed and two n-type active regions 304a and 304b in which pMOS transistors are formed. Each of the active regions 302a, 302b, 304a, and 304b is surrounded by a device isolation insulating region of, for example, a LOCOS (Local Oxidation of Silicon) or trench structure.
In the SRAM cell 300 of the related art, each of the two p-type active regions 302a and 302b has a shape in a plan view which is bent outward almost at a right angle. A driving transistor Qn1 (or Qn2) and a word transistor Qn3 (or Qn4) are formed on both sides of the bent part. A word line WL serving as a polysilicon gate electrode of each of the word transistors Qn3 and Qn4 almost perpendicularly crosses the two p-type active regions 302a and 302b and penetrates the cell in the lateral direction in FIG. 27. On the other hand, common gate lines 306a and 306b serving as polysilicon gate electrodes of the driving transistors Qn1 and Qn2 are individually provided in every cell. That is, the common gate line 306a perpendicularly crosses the p-type active region 302a in the vertical direction of FIG. 27. In a similar direction, the common gate line 306b perpendicularly crosses the p-type active region 302b.
The common gate lines 306a and 306b also perpendicularly cross the n-type active regions 304a and 304b, respectively. The pMOS transistors (load transistors Qp1 and Qp2) are formed in the n-type active regions 304a and 304b, respectively. A first inverter is formed by the load transistor Qp1 and the driving transistor Qn1. Similarly, a second inverter is formed by the load transistor Qp2 and the driving transistor Qn2. Each of the common gate lines 306a and 306b is branched at some midpoint. As shown by connecting lines in FIG. 27, the input terminal of one of the inverters is connected to the output terminal of the other inverter in the second polysilicon wiring layer. A supply line of a power source voltage V.sub.cc, supply line, a common potential V.sub.ss supply line, and bit lines BL1 and BL2 are connected as shown in the diagram.
[Related Art 2]
In recent years, a split word line type SRAM cell in which word lines are arranged so as to be isolated from every word transistor has been proposed in, for example, "A low Cost Microprocessor Compatible, 18.4 .mu.m.sup.2, 6-T Bulk Cell Technology for High Speed SRAMs", VLSI Symposium Report, pp 65-66, 1993.
FIG. 28 is a plan view, in a manner similar to FIG. 27, showing an arrangement pattern of a split word line type cell described in the literature.
In a split word line type SRAM cell 310, a p-type active region 312 in which nMOS transistors are formed is provided so as to be commonly used by inverters and word transistors and is also commonly used by cells neighboring in the word line direction. Similarly, an n-type active region 314 in which pMOS transistors are formed is commonly formed in between each inverter and in between each cell neighboring in the word line direction. The connecting lines shown in FIG. 28 are basically similar to those in FIG. 27. A p-MOS transistor and an n-MOS transistor of each inverter are connected in series in the second polysilicon layer. A connecting part of the series connection point of the p-MOS and n-MOS transistors and the input terminal of another inverter, the power source voltage V.sub.cc supply line and the like are formed in the third polycide layer. The common potential V.sub.ss supply line and the bit lines are formed in the fourth metal wiring layer.
Generally, in order to increase the packing density and the capacity of a semiconductor memory device, it is indispensable to make a finer pattern. The formation of a finer pattern can be achieved by making a pattern itself finer and introduction of a self aligning formation technique which does not require a reduction in a deviation amount in alignment of photo masks in different patterns and improvement on an alignment deviation between patterns.
The former technique of making a pattern itself finer is achieved by improving the material of a resist, increasing a process accuracy of wiring and the like which are formed by using the resist as a pattern transfer mask and shortening the wavelength of light from the light source of an aligner from the g and i lines, a KrF excimer laser, an Ar excimer laser, and further to an X-ray.
On the other hand, with respect to the alignment deviation among patterns in the latter technique, by applying the self aligning formation technique, the alignment deviation can be largely reduced while assuring good characteristics and high reliability. In an actual device manufacture, however, processes to which the self aligning formation technique can be applied are limited. In the other processes, the deviation among patterns depends on the machine accuracy of the aligner. Since the machine accuracy has not been improved largely, under the present circumstances, the reduction in the amount of deviation has not progressed as much as the reduction in size of the pattern.
A pattern design such that even when a deviation occurs in the alignment of patterns during a process to which the self aligning technique cannot be applied, the deviation does not become a problem from the viewpoint of characteristics, reliability, and the like is demanded.
In the SRAM cells of the related arts 1 and 2 shown in FIGS. 27 and 28, however, the deviation among patterns is not sufficiently considered in the pattern design.
For example, in the SRAM cell 300 of the related art 1 shown in FIG. 27, each of the p-type active regions 302a and 302b in which the nMOS transistors are formed bends outward. Although the pattern on the mask is a combination of rectangles, as illustrated in the diagram, an actual finished pattern is deformed with the corners largely rounded. This is caused by excessive light intensity in the case of pattern formation by leaving a resist or by insufficient light intensity in the case of pattern formation by removing a resist when exposure is performed by using a mask pattern (pattern transfer) onto the resist. In the specifically shown example, the gate width (i.e., the size of an overlapped part in the direction which perpendicularly crosses the channel current direction) of each of the driving transistors Qn1 and Qn2 tends to increase and the gate width of each of the word transistors Qn3 and Qn4 tends to decrease.
In addition to the pattern deformation, the patterns themselves of the p-type active regions 302a and 302b are bent and the transistor size (i.e., the size of the channel forming region) varies due to the deviation of the photo mask when gate electrodes (in this case, the word line WL and the common gate lines 306a and 306b) are formed on the patterns. For instance, in FIG. 27, when the gate pattern such as common gate lines 306a and 306b is deviated to the right side with respect to the pattern of the p-type active regions 302a and 302b (LOCOS pattern in practice), the gate width of the driving transistor Qn2 decreases and the gate width of the driving transistor Qn1 increases. On the contrary, when the gate pattern is deviated to the left side, the gate width of the driving transistor Qn1 decreases and the gate width of the driving transistor Qn2 increases. In any case, the characteristics of the two inverters constructing the flip-flop become accordingly unequal. Thus, the stability of the flip-flop and further the data holding characteristics of the SRAM memory cell deteriorate.
When the gate pattern is deviated downward, the gate width of each of the word transistors Qn3 and Qn4 is reduced. At the time of reading or writing data from/to the SRAM memory cell, especially on the low node side maintained at a low potential level, the resistance in a current path of the cell current flowing from the bit line, word transistor, storage node, driving transistor, and to the common potential supplying line becomes high and the reading or writing operation becomes slow. On the contrary, when the gate pattern is deviated upward, although there does not occur any problem in the cell shown in FIG. 27, a similar problem which occurs when the gate pattern is deviated downward occurs in an upper cell which is adjacent to the cell of FIG. 27. The cells are arranged to be symmetrical in the vertical direction with respect to the bit contacts as a center. As a result, the resistance in the cell current path increases and the reading or writing operation becomes slow.
As described above, when the size on the nMOS transistor side changes, that is, when the sizes of the driving transistor and the word transistor change relatively, the cell characteristics (i.e., data holding characteristic, high speed, and the like) deteriorate. The deviation among patterns slightly varies according to a position in a wafer (for example, every chip), the characteristics also change according to the position in the wafer. This appears as a characteristic variation of semiconductor products, occurring in memory cell arrays or chips.
The problem of the deterioration and variation in the characteristics due to the variation in transistor size also occurs in the split word line type SRAM cell illustrated in FIG. 28. In the split word line type SRAM cell 310, the active regions 312 and 314 are commonly connected to neighboring cells and the common connection part is bent with respect to the other part. Consequently, the size change becomes a problem in both of the driving transistors Qn1 and Qn2 and the load transistors Qp1 and Qp2 which are adjacent to the bent part. Especially, the SRAM cell of this type is sensitive to the deviation in the bit line wiring direction and a variation tends to occur among inverters. The data holding characteristic of the memory cell deteriorates in this case as well, and the reading or writing speed becomes lower.
As another related art, "A Novel 6.4 .mu.m.sup.2 Full-CMOS SRAM Cell with Aspect Ratio of 0.63 in a High-Performance 0.25 .mu.m-Generation CMOS Technology", 1998 Symposium on VLSI Technology Digest of Technical Papers discloses a pattern for a high speed SRAM. Since the SRAM has a region in which an active region is bent, it has also a problem similar to that of the related arts.
The problem of the deterioration and variation in the characteristics can be avoided by sufficiently separating the gate electrode from the bent part in the active region. It is not, however, preferable since the cell area increases.
The applicant of the present invention has consequently proposed a cell pattern and a semiconductor memory device having a cell structure which can effectively prevent the deterioration in the characteristics due to a deviation in patterns at the time of forming the gate while effectively suppressing enlargement of the memory cell area or, moreover, reducing the memory cell area (Japanese Unexamined Patent Application No. 10-171186). The outline of the semiconductor memory device will now be described hereinbelow.
FIGS. 29 to 32 show pattern structures and cross sections in processes of fabricating the SRAM cell 200 as an example of the semiconductor memory device which has been proposed before.
In a state shown in FIG. 29, a device isolation region 202 such as LOCOS or trench is formed on the surface side of a semiconductor substrate 201 such as a silicon wafer in which a p-type well region and an n-type well region (not shown) are formed. The surface region of the p-type well region in which the device isolation region 202 is not formed is a p-type active region 203 in which an n-type MOS channel is formed. The surface region of the n-type well region in which the device isolation region 202 is not formed is an n-type active region 204 in which a pMOS channel is formed. The two active regions 203 and 204 each having a rectangular pattern are formed in parallel. FIG. 30 is a cross section taken along the line M-M' of FIG. 29.
In the process shown in FIG. 32, after performing ion implantation for threshold voltage control or channel stopper as required, a gate oxide film 205, a first polysilicon or polycide layer (hereinbelow, referred to as "1PS"), and an offset insulating film 208 are sequentially formed. The 1PS is comprised of, for example, a polysilicon film 206 and a WSix film 207. The gate oxide film 205 and the offset insulating film 208 are made of oxide silicon. The thickness of each of the polysilicon film 206 and the WSix film 207 is about 70 nm. The thickness of the offset insulating film 208 is about 200 nm. By introducing impurities at the time of or after the film formation, the polysilicon film 206 is made conductive.
Subsequently, the offset insulating film 208, the WSix film 207, the polysilicon film 206, and the gate oxide film 205 are successively processed, thereby simultaneously forming two word lines WL1 and WL2 also serving as gate electrodes of two word transistors, a common gate line GL1 also serving as gate electrodes of the driving and load transistors, and a common gate line GL2 also serving as gate electrodes of the driving and load transistors.
The two word lines WL1 and WL2 perpendicularly cross near both ends of the p-type active region 203, penetrate the cells, and are arranged in parallel to each other. The common gate lines GL1 and GL2 perpendicularly cross both of the p-type active region 203 and the n-type active region 204 within the interval of the word lines WL1 and WL2 and are arranged in parallel to each other so that the common gate lines GL1 and GL2 and the word lines WL1 and WL2 are spaced at regular intervals. Each of the common gate lines GL1 and GL2 has a rectangular pattern provided for every cell and is isolated from common gate lines (not illustrated) of cells neighboring in the word line direction. FIG. 32 is a cross section taken along the line N-N' of FIG. 31.
In the SRAM cell having such a structure, each of the two active regions 203 and 204 in the cell is formed in a simple rectangular pattern or a pattern of an almost rectangular shape with a step so that the channel current directions are in parallel. Gate electrode patterns (word lines WL1 and WL2 and the common gate lines GL1 and GL2) formed on the active regions 203 and 204 are arranged in parallel to each other. Due to a deviation in alignment at the time of formation of the gate electrode patterns, therefore, the size of the transistor (i.e., the size of the area in which the gate electrode pattern and the active area is overlapped) uniformly changes in transistors. As for the alignment, there is the possibility that not only a pattern deviation in the xy directions but also a rotation deviation (deviation 0) occurs. Due to any of the xy direction deviation and the deviation 0, the sizes of all transistors uniformly change. Especially, since the pattern does not have the bent active region unlike the conventional pattern, it is not easily influenced by a distortion in the pattern shape caused by excessive or insufficient exposure intensity. That is, as long as there is not a large alignment deviation to the ends of the active areas 203 and 204 as rectangular patterns, the situation such that the size of only a specific transistor changes as in the related arts can be effectively avoided.
Since the transistor characteristics in the cells do not vary due to the alignment deviation in the patterns, the inverter characteristics of the memory cell are therefore stabilized. Various effects such that the charge holding characteristics of the SRAM cell do not deteriorate during a manufacturing process and excellent cell characteristics are obtained can be produced.
Although the excellent effects as described above can be obtained, since memory cells are arranged bit by bit in the vertical direction (that is, the word and bit line directions) in a matrix state, the SRAM cell has a problem such that it is difficult to further increase the packing density.